This invention relates to an arbiter circuit and an associated method for determining access to a system resource in a system that has at least three signals seeking access to the resource, a first one of which must have access at predetermined periodic intervals to the exclusion of any of the other signals, and at least two other of the signals being capable of maintaining access on a mutually exclusive basis for an indefinite period of time that may be longer than one of the predetermined periodic intervals.
The concept of applying three or more signals to separate input terminals of a single arbiter that can determine which of the three signals, if they are all submitted simultaneously so as to interfere with each other, can pass through the arbiter circuit and obtain access to a common part of a following circuit, such as the memory in a computer, is well known. One way of arbitrating contention among three such signals is simply to enable each input circuit in turn. One difficulty of such a procedure is that, if no signal is being applied at a given time to one of the input terminals, as will frequently be the case, any time lost in enabling that input terminal will unnecessarily slow down the operation of the overall system.
Another, and potentially more significant problem arises from the fact that the nature of signals applied to the system resource, and especially to a memory frequently have three subintervals, or cycles. One is a cycle in which information at a given memory location is read. A second is a cycle in which either that information or a flag bit that determines access to the memory is modified. The third is a writing cycle,in which new information is written into a given memory location. Such read-modify-write (RMW) cycles must be carried out in unitary fashion so that the system resource must be interactively latched to a given input terminal from the beginning of the read cycle to the end of the write cycle. Frequently the operation is such that the input circuit ceases to control access to the memory during the modify portion of the RMW cycle, and it is then possible for another signal, applied by way of another input circuit, to latch onto access to the memory. If that happens, the information received through the second input terminal can be applied as a signal to be written into the first address, which would be completely incorrect.
Another problem is that any one of the signals can have a duration that will lock out the other signals for a very long period of time. This can be especially troublesome if the common circuit element to which access is sought is a dynamic random access memory (DRAM) that operates on the basis of storage of an electric charge that can leak off after a certain interval of time and must be refreshed within that interval in order for the system to operate properly. It is unacceptable for another signal that does not have the effect of refreshing the memory, except for that part of the memory that may be used by such other signal, to latch onto control of the access to the DRAM for a period of time longer than the refresh interval.
It is one of the objects of the present invention to provide a high-speed system and a method for separating arbitration among different signals so that arbitration between two or more of the signals that, as between themselves, can maintain control of access to a system resource for an indeterminately long period of time, can be determined in a first arbiter, with the successful signal then contending in a second arbiter with a signal that must have access to the system resource at some time within each periodic interval.
Another object of the invention, in which the winning signal of the first arbitration is divided into two or more active intervals separated by one or more inactive intervals, is to arrange for the second arbitration to allow the signal that must have periodic access to have such access at the end of each active interval, or transaction, of the successful signal.
A further object of the invention is to interrupt the operation of the first arbiter after the lapse of a certain length of time if the signal that has obtained control of the first arbiter and is therefore the winning signal for submission to the second arbiter, appears not to be operating correctly, as, for example, would be true if the controlling signal were not broken up into short transactions.
Further objects will become apparent from the teachings of the following specification, taken together with the drawings.